Broadcom Ships Industry's First 2nm 3.5D Custom AI Chip to Fujitsu

The race for AI infrastructure dominance has entered a new dimension—literally. On February 26, 2026, Broadcom Inc. announced that it has commenced shipping the industry's first 2nm custom compute System-on-Chip (SoC) to its lead partner, Fujitsu. This shipment represents more than just a hardware update; it is the debut of Broadcom’s 3.5D eXtreme Dimension System in Package (XDSiP) platform, a technology designed to solve the massive power and latency bottlenecks currently throttling global AI clusters.

As enterprises move from experimental AI pilots to massive, production-grade deployments, the demand for "XPUs"—customized accelerators tailored for specific workloads—has skyrocketed. Broadcom’s new 2nm silicon is the cornerstone of this shift, offering a level of integration and energy efficiency that traditional 2D or even 2.5D designs can no longer provide.

The 3.5D Breakthrough: Stacking for Success

What differentiates this chip is the "Face-to-Face" (F2F) technology. By stacking two pieces of silicon directly on top of one another, Broadcom has enabled data to flow between compute and memory layers with unprecedented speed. Harish Bharadwaj, Broadcom’s Vice President of Product Marketing, noted in an exclusive interview with Reuters that this stacking approach delivers approximately 10 times better energy performance compared to traditional side-by-side designs.

The technical specifications are equally staggering. The Fujitsu chip fuses a cutting-edge 2nm process node with a 5nm chip, both fabricated by TSMC. This "mix-and-match" capability allows customers to optimize costs by using the most expensive 2nm silicon only where it is needed most, such as the core compute engine, while keeping peripheral components on more mature, cost-effective nodes.

Powering the "FUJITSU-MONAKA" Initiative

For Fujitsu, this delivery is a critical enabler for its FUJITSU-MONAKA initiative. The goal is to produce a new generation of high-performance, low-power processors that can handle the "gigawatt-scale" requirements of modern data centers without triggering an energy crisis. Naoki Shinjo, SVP and Head of Advanced Technology Development at Fujitsu, described the launch as a "transformative milestone" that unlocks the compute density essential for the next era of High-Performance Computing (HPC) and AI.

Key advantages of this new architecture include:

• Independent Scaling: The XDSiP platform allows compute, memory, and network I/O to scale independently, offering a "build-your-own" flexibility for enterprise giants.

• Unparalleled Signal Density: Stacking the dies reduces the physical distance data must travel, virtually eliminating the latency issues found in sprawling multi-chip modules.

• Thermal Management: Despite the density, the 3.5D design is engineered for both air and liquid cooling, making it compatible with existing green data center infrastructures.

A Global Rollout Strategy

Broadcom isn't stopping with a single partnership. The company has already signaled that it expects to ship 3.5D-based XPUs to its wider customer base starting in the second half of 2026. With a target of selling at least 1 million 3D stacked chips by 2027, Broadcom is positioning itself as the primary alternative to Nvidia for firms looking to build in-house, custom-silicon solutions.

As noted by Broadcom’s official investor relations, the expansion of the platform is already supporting several other high-complexity designs currently in the sampling phase. This aggressive roadmap suggests that the industry's reliance on "off-the-shelf" GPUs may soon be tempered by a wave of bespoke, energy-efficient silicon designed for the specific needs of the world’s largest hyperscalers.

In a market where power consumption has become the ultimate constraint on growth, Broadcom’s 3.5D innovation isn't just a technical win—it's a commercial necessity for the sustainable future of artificial intelligence.